OffsetOut

A UGen that writes a signal onto a bus, delaying the signal such that the input will begin to appear on the bus precisely when the encompassing Synth was scheduled according to its OSC bundle. I.e. if the synth is scheduled to be started part way through a control cycle, OffsetOut will maintain the correct offset by buffering the output and delaying it until the exact time that the synth was scheduled for.

This UGen adds ("mixes") the input-signal to the existing contents of the bus.

Multi-channel input signals, for example a PanAz , are written as such to the bus without expansion. That is, the bus index argument is used for the first channel, the second channel will appear on bus + 1 , etc.

If you have an expanding multi-channel input, however, you have to be careful. For example, if you have PanAz.ar(2, SinOsc.ar(Seq(444, 555, 666)) * 0.2, Seq(-1, 0, 1)) , this results in one output UGen carrying one channel, and another one carrying two channels. (The way this works is consistent with SCLang). In order to get the correct behaviour (left outputs of the PanAz summed, and right output of the PanAz summed), wrap this expression in a Mix(...) before passing it to the output UGen.

Note: You cannot currently achieve sample accurate scheduling in SuperCollider. This UGen is therefore more or less useless.

Examples

// compare left-right
val sd = SynthDef.recv("offset-out") {
  val x = Impulse.ar(2)
  val y = SubsampleOffset.ir
  y.poll(0, "offset")
  Out      .ar(0, x)
  OffsetOut.ar(1, x)    // right channel will be delayed against left
}

val x = Synth(s)
s ! osc.Bundle.millis(System.currentTimeMillis + 1000, x.newMsg(sd.name, s))

See also: SubsampleOffset
XOut
ReplaceOut
Out

Linear Supertypes

Serializable, Serializable, AnyRef, Any

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
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final def ##(): Int

Definition Classes
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final def ==(arg0: Any): Boolean

Definition Classes
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def ar(bus: GE, in: GE): OffsetOut

bus
bus index to write to. For an audio-rate UGen, this is an audio-bus, for a control-rate UGen, this is a control-bus.
in
signal to write to the bus. If the UGen is audio-rate, the input must also be audio-rate.
final def asInstanceOf[T0]: T0

Definition Classes
Any
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
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@throws( ... )
final def eq(arg0: AnyRef): Boolean

Definition Classes
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def equals(arg0: Any): Boolean

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def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
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@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
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def hashCode(): Int

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final def isInstanceOf[T0]: Boolean

Definition Classes
Any
final def ne(arg0: AnyRef): Boolean

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final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
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final def synchronized[T0](arg0: ⇒ T0): T0

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def toString(): String

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final def wait(): Unit

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@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

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@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
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@throws( ... )

Related Docs: class OffsetOut | package ugen

object OffsetOut extends Serializable

Examples

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def ar(bus: GE, in: GE): OffsetOut

final def asInstanceOf[T0]: T0

def clone(): AnyRef

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from Serializable

Inherited from Serializable

Inherited from AnyRef

Inherited from Any

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