the input signal to gate
the signal specifying whether to pass the input signal (when greater than zero) or whether to close the gate and hold the last value (when less than or equal to zero)
the input signal to gate
the signal specifying whether to pass the input signal (when greater than zero) or whether to close the gate and hold the last value (when less than or equal to zero)
A gate or hold UGen. It allows the input signal value to pass when the
gate
argument is positive, otherwise it holds last value.Before the first high gate value is registered, this UGen outputs zero.
Latch